1/9 preliminary data february 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. STB60NH02L n-channel 24v - 0.0085 w - 60a d2pak stripfet? iii power mosfet n typical r ds (on) = 0.0085 w @ 10 v n typical r ds (on) = 0.012 w @ 5 v n r ds(on) * qg industrys benchmark n conduction losses reduced n switching losses reduced n low threshold device n surface-mounting d 2 pak (to-263) power package in tube (no suffix) or in tape & reel (suffix t4 description the STB60NH02L utilizes the latest advanced design rules of sts proprietary stripfet? technology. this is suitable fot the most demanding dc-dc converter application where high efficiency is to be achieved. applications n specifically designed and optimised for high efficiency dc/dc convertes type v dss r ds(on) i d STB60NH02L 24 v < 0.0105 w 60 a 1 3 d 2 pak to-263 (suffix t4) absolute maximum ratings symbol parameter value unit v spike(1) drain-source voltage rating 30 v v ds drain-source voltage (v gs = 0) 24 v v dgr drain-gate voltage (r gs = 20 k w ) 24 v v gs gate- source voltage 20 v i d drain current (continuous) at t c = 25c 60 a i d drain current (continuous) at t c = 100c 43 a i dm (2) drain current (pulsed) 240 a p tot total dissipation at t c = 25c 60 w derating factor 0.4 w/c e as (3) single pulse avalanche energy 280 mj t stg storage temperature -55 to 175 c t j max. operating junction temperature internal schematic diagram
STB60NH02L 2/9 thermal data electrical characteristics (t case = 25 c unless otherwise specified) off on (4 ) dynamic rthj-case rthj-amb t l thermal resistance junction-case thermal resistance junction-ambient maximum lead temperature for soldering purpose max max 2.5 62.5 300 c/w c/w c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 25 ma, v gs = 0 24 v i dss zero gate voltage drain current (v gs = 0) v ds = 20 v v ds = 20 v t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 1 1.8 v r ds(on) static drain-source on resistance v gs = 10 v i d = 30 a v gs = 5 v i d = 15 a 0.0085 0.012 0.0105 0.020 w w symbol parameter test conditions min. typ. max. unit g fs (4) forward transconductance v ds = 20 v i d = 25 a 10 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 15v f = 1 mhz v gs = 0 1400 400 55 pf pf pf r g gate input resistance f = 1 mhz gate dc bias = 0 test signal level = 20 mv open drain 1 w
3/9 STB60NH02L switching on switching off source drain diode (1) garanted when external rg=4.7 w and t f < t fmax . (4) pulsed: pulse duration = 300 s, duty cycle 1.5 %. (2) pulse width limited by safe operating area (5) q oss = c oss * d v in , c oss = c gd + c ds . see appendix a ( 3 ) starting t j = 25 o c, i d = 25a, v dd = 15v . . symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 10 v i d = 30 a r g = 4.7 w v gs = 10 v (resistive load, figure 3) 10 130 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 10 v i d = 60 a v gs = 10 v 24 5 3.4 32 nc nc nc q oss (5) output charge v ds = 16 v v gs = 0 v 9.4 nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 10 v i d = 30 a r g = 4.7 w, v gs = 10 v (resistive load, figure 3) 27 16 21.6 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm (2) source-drain current source-drain current (pulsed) 60 240 a a v sd (4) forward on voltage i sd = 30 a v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 60 a di/dt = 100a/s v dd = 18 v t j = 150c (see test circuit, figure 5) 36 36 2 ns nc a electrical characteristics (continued)
STB60NH02L 4/9 fig. 1: unclamped inductive load test circuit fig. 1: unclamped inductive load test circuit fig. 2: unclamped inductive waveform fig. 3: switching times test circuits for resistive load fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times
5/9 STB60NH02L dim. mm. inch. min. typ. max. min. typ. typ. a 4.4 4.6 0.173 0.181 a1 2.49 2.69 0.098 0.106 a2 0.03 0.23 0.001 0.009 b 0.7 0.93 0.028 0.037 b2 1.14 1.7 0.045 0.067 c 0.45 0.6 0.018 0.024 c2 1.21 1.36 0.048 0.054 d 8.95 9.35 0.352 0.368 d1 8 0.315 e 10 10.4 0.394 0.409 e1 8.5 0.334 g 4.88 5.28 0.192 0.208 l 15 15.85 0.591 0.624 l2 1.27 1.4 0.050 0.055 l3 1.4 1.75 0.055 0.069 m 2.4 3.2 0.094 0.126 r 0.4 0.015 v2 0 8 0 8 d 2 pak mechanical data
STB60NH02L 6/9 dim. mm inch min. max. min. max. a0 10.5 10.7 0.413 0.421 b0 15.7 15.9 0.618 0.626 d 1.5 1.6 0.059 0.063 d1 1.59 1.61 0.062 0.063 e 1.65 1.85 0.065 0.073 f 11.4 11.6 0.449 0.456 k0 4.8 5.0 0.189 0.197 p0 3.9 4.1 0.153 0.161 p1 11.9 12.1 0.468 0.476 p2 1.9 2.1 0075 0.082 r50 1.574 t 0.25 0.35 .0.0098 0.0137 w 23.7 24.3 0.933 0.956 dim. mm inch min. max. min. max. a 330 12.992 b 1.5 0.059 c 12.8 13.2 0.504 0.520 d 20.2 0.795 g 24.4 26.4 0.960 1.039 n 100 3.937 t 30.4 1.197 base qty bulk qty 1000 1000 reel mechanical data * on sales type tube shipment (no suffix)* tape and reel shipment (suffix t4)* d 2 pak footprint tape mechanical data
7/9 STB60NH02L sw1 sw2 appendix a buck converter: power losses estimation the power losses associated with the fets in a synchronous buck converter can be estimated using the equations shown in the table below. the formulas give a good approximation, for the sake of performan ce comparison, of how different pairs of devices affect the converter efficiency. however a very important parameter, the working temperature, is not considered. the real device behavior is really dependent on how the heat generated inside the devices is r emoved to allow for a safer working junction temperature. the low side ( sw2 ) device requires: very low r ds(on) to reduce conduction losses small q gls to reduce the gate charge losses small c oss to reduce losses due to output capacitance small q rr to reduce losses on sw 1 during its turn-on the c gd /c gs ratio lower than v th /v gg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; the high side ( sw1) device requires: small r g and l s to allow higher gate current peak an d to limit the voltage feedback on the gate small q g to have a faster commutation and to reduce gate charge losses low r ds(on) to reduce the conduction losses.
STB60NH02L 8/9 high side switch (sw1) low side switch (sw2) conduction p d * i * r 2 l ds(on)sw1 ) 1 ( * i * r 2 l ds(on)sw2 d - switching p g l i i * f * ) q (q * v gd(sw1) gsth(sw1) in + zero voltage switching recovery not applicable 1 f * q * v rr(sw2) in diode p conduction not applicable f * t * i * v deadtime l f(sw2) ) gate(q g p f * v * q gg g(sw1) f * v * q gg gls(sw2) qoss p 2 f * q * v oss(sw1) in 2 f * q * v oss(sw2) in parameter meaning d duty- cycle q gsth post threshold gate charge q gls third quadrant gate charge pconduction on state losses pswitching on-off transition losses pdiode conduction and reverse recovery diode losses pgate gate drive losses qoss p output capacitance losses 1 dissipated by sw1 during turn-on
9/9 STB60NH02L information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com
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